A Proficient Low Power Logarithmic Multiplier Using Iterative Pipeline Technique

Multiplication is the basic function performed in digital signal processors (DSP) and multimedia processors. Applications in DSP heavily rely on multiplication with high performance as a prime target but the major requirement is complex data handling. So, logarithmic multiplier is a practical solution for DSP functions that performs multiplication using simple addition operation. The LNS system offers speed, cost and delay at the expense of accuracy. Thus, they are most suitable for DSP applications which have the capacity to tolerate errors at minimal errors. This paper presents 16-bit logarithmic multiplier based on the Mitchell’s algorithm. This multiplier is designed with four error correction circuits using iterative pipeline technique to achieve a arbitrary accuracy with low power consumption. The proposed design reduces the maximum relative error to 0.029%, which is tolerable in DSP applications. The proposed architecture is simulated in VHDL by using ISIM simulator of XST (Xilinx synthesis Tool) at 25MHz frequency using device 3 xc3s1500-5fg676 FPGA chip. KeywordsLogarithmic multiplier; Logarithmic number system; Multiplier; Digital signal processing etc.